A Low-latency Routerless On-chip Network Design for Many-core Processors and Accelerators

Summary

Technology Description

 

The proposed design does not have any on-chip routers, hence it is called routerless design. It also incorporates a layered network which is a mesh like structure that allows the packets to be sent to various core locations. The routerless NoC design also includes circles, traditionally known as rings which ensure an optimal hop count. A low average hop count is optimal because this ensures that the packets need not traverse long distances to reach their destination. This in turn is essential in saving power costs. The circles are also important features because they ensure that the packets can get from one section to another and are reusable. Through these innovative components, the routerless design provides a better NoC alternative than any of the current NoC designs used in CMPs today.

 

Features & Benefits

 

  • Improved Efficiency
  • Lower Power Usage
  • Simple Design

 

Applications

 

  • Multicore chip processors
  • Personal and mobile computing

 

Background of Invention

 

Many electronic devices such as laptops depend on a Chip Multi-Processor (CMP). A chip multi-processor is a computing unit with multiple cores that is essential to the functioning of the device. The architecture of a chip multi-processor is a Net¬work-on-Chip (NoC) design. A NoC design is necessary to communicate among the multiple cores of the CMP. Most NoC designs used today choose flexibility over efficiency. The current NoC designs are very scalable, latent and saturated but they have high costs in area and power. Routers are used in NoC designs to offer flexibility and avoid congestion among the routes since the faster a packet is delivered the more resources are saved. This technology addresses the loss of efficiency by proposing a routerless layered design that provides high flexibility and high efficiency.

 

Status

 

Laboratory tested, ready for further development. Provisional patent application filed.

 

 

Patent Information:
Tech ID:
OSU-16-09
Category(s):
Device
Contact:
David Dickson
IP & Licensing Manager
Oregon State University
541-737-3450
david.dickson@oregonstate.edu
Inventors:
Lizhong Chen
Fawaz Alazemi
Bella Bose
Keywords:
Electrical & Computer Engineering
Many-core processors
On-chip Networks
Routerless
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