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A Low-latency Routerless On-chip Network Design for Many-core Processors and Accelerators
Technology Description The proposed design does not have any on-chip routers, hence it is called routerless design. It also incorporates a layered network which is a mesh like structure that allows the packets to be sent to various core locations. The routerless NoC design also includes circles, traditionally known as rings which ensure an optimal...
Published: 9/14/2016   |   Inventor(s): Lizhong Chen, Fawaz Alazemi, Bella Bose
Keywords(s): Electrical & Computer Engineering, Many-core processors, On-chip Networks, Routerless
Category(s): Device
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