Method and Tool for Automated Insertion of Low Voltage Swing Signaling Drivers and Receivers for Design Energy or Timing Improvement

Summary

 

Technology Description

 

LVS Cell Insertion is an automated procedure that can be summarized into three general steps. Firstly, the design is analyzed to determine potential energy reduction, and area/timing overheads. Following that, analysis reports are generated and presented that allow a designer to optimize the LVS procedure for their particular priorities. Finally, the necessary ECO commands within the context of the original design flow are generated to insert and replace LVS cells in the original design based on the previous steps.

 

Features & Benefits

 

  • Cut up to 15% of the energy consumption of a design
  • Minimal additional design effort
  • Low risk: can take in set of completed design filed and produce an optimized set, but if the results from the optimized design are not sufficient, the original design can still be used

 

Applications

 

  • Digital ICs

 

Background of Invention

 

Digital integrated circuit technology is constantly improving. Conventional CMOS circuitry has been increasing transistor density, continually reducing the energy consumed by computation. However, a problem has arisen within the field concerning the energy and delay associated with on-chip wires. In recent microprocessors, the energy cost of transporting data on-chip has been greater than that needed to perform a computation, even across relatively short wires. LVS signaling has been explored as a method of reducing signaling latency and energy on on-chip wires. Up to this point in time, implementation of LVS circuits in a conventional digital design flow has required significant manual design and verification effort, and has generally been impractical. Use of these circuits for on-chip wire signaling has been limited to only the most obvious long, global wire routes in academic designs. Researchers at Oregon State University have developed a LVS Cell insertion process that provides an automated procedure for implementing LVS signaling on on-chip wires within an existing conventional digital design flow.

 

Status

 

US Patent Application 13/956,140

Patent Information:
Tech ID:
OSU-12-32
Category(s):
Software
Contact:
Denis Sather
Senior IP & Licensing Manager
Oregon State University
541-737-4437
denis.d.sather@oregonstate.edu
Inventors:
Patrick Chiang
Jacob Postman
Keywords:
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